fn9075 rev 8.00 page 1 of 10 december 2, 2005 fn9075 rev 8.00 december 2, 2005 isl6207 high voltage synchronous rectified buck mosfet driver datasheet the isl6207 is a high freq uency, dual mosfet driver, optimized to drive two n-ch annel power mosfets in a synchronous-rectified buck conv erter topology in mobile computing applications. this dr iver, combined with an intersil multi-phase buck pwm controller , such as isl6223, isl6215, and isl6216, forms a complete single-stage core-voltage regulator solution for advan ced mobile microprocessors. the isl6207 features 4a typical sink current for the lower gate driver. the 4a typical sink cu rrent is capable of holding the lower mosfet gate during the phase node rising edge to prevent the shoot-through power loss caused by the high dv/dt of the phase node. the operation voltage matches the 30v breakdown voltage of the mosfets commonly used in mobile computer power supplies. the isl6207 also features a t hree-state pwm input that, working together with most of intersil multiphase pwm controllers, will prevent a neg ative transien t on the output voltage when the out put is being shut down. this feature eliminates the schottky diode, that is usually seen in a microprocessor power syste m for protecting the microprocessor, from revers ed-output-voltage damage. the isl6207 has the capacity to efficiently switch power mosfets at frequencies up to 2mhz. each driver is capable of driving a 3000pf load with a 15ns propagation delay and less than a 10ns trans ition time. this product implements bootstrapping on the up per gate with an in ternal bootstrap schottky diode, reducing impl ementation cost, complexity, and allowing the use of higher performance, cost effective n-channel mosfets. adaptive s hoot-through protection is integrated to prevent both mosfets from conducting simultaneously. features ? drives two n-channel mosfets ? adaptive shoot-through protection ? 30v operation voltage ?0.4 ? on-resistance and 4a s ink current capability ? supports high switching frequency - fast output rise time - short propagation delays ? three-state pwm input for power stage shutdown ? internal bootstrap schottky diode ? qfn package: - compliant to jedec pub95 mo-220 qfn - quad flat no leads - package outline - near chip scale package footprint, which improves pcb efficiency and has a thinner profile ? pb-free plus anneal available (rohs compliant) applications ? core voltage supplies for intel and amd ? mobile microprocessors ? high frequency low prof ile dc/dc converters ? high current low output v oltage dc/dc converters ? high input voltage dc/dc converters related literature ? technical brief tb363 guidelines for handling and processing moisture sensit ive surface mount devices (smds) ? technical brief tb389 pcb land pattern design and surface mount guidelines for qfn packages pinouts isl6207 (soic-8) top view isl6207 (qfn) top view ugate boot pwm gnd 1 2 3 4 8 7 6 5 phase en vcc lgate 7 ugate phase 8 4 3 1 2 6 gnd lgate en vcc boot pwm 5 6 n o t r e c o m m e n d e d f o r n ew d e si g n s n o r e c o m m e n d e d r ep l a c e m en t c o n t a c t o u r t e c h n i c a l s u p p o r t c e n te r a t 1 -8 8 8 -i n t e r s i l o r w w w . i n te r s i l . c o m / t s c
isl6207 fn9075 rev 8.00 page 2 of 10 december 2, 2005 isl6207 block diagram ordering information part number part marking temp. range (c) package pkg. dwg. # isl6207cb isl6207cb -10 to 85 8 lead soic m8.15 isl6207cbz (note) isl6207cbz -10 to 85 8 lead soic (pb-free) m8.15 isl6207cbza (note) isl6207cbz -10 to 85 8 lead soic (pb-free) m8.15 isl6207cr 207c -10 to 85 8 lead 3x3 qfn l8.3x3 isl6207crz (note) 07cz -10 to 85 8 lead 3x3 qfn (pb-free) l8.3x3 isl6207crza (note) 07cz -10 to 85 8 lead 3x3 qfn (pb-free) l8.3x3 ISL6207HBZ (note) ISL6207HBZ -10 to 100 8 ld soic (pb- free) m8.15 isl6207hrz (note) 07hz -10 to 100 8 ld 3x3 qfn (pb-free) l8.3x3 add -t suffix for tape and reel. note: intersil pb-free plus anneal products employ special pb-fr ee material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and comp atible with both snpb and pb-free sol dering operations. intersil pb-fr ee products are msl classified at p b-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. vcc pwm vcc 10k 10k control logic shoot- through protection boot ugate phase lgate gnd vcc en thermal pad (for qfn package only)
isl6207 fn9075 rev 8.00 page 3 of 10 december 2, 2005 typical application - two phase con verter using isl6207 gate drivers +5v boot ugate phase lgate pwm en vcc drive v bat +5v boot ugate phase lgate pwm v bat +v core pgood vid fs gnd isen2 isen1 pwm2 pwm1 vsen main fb vcc +5v comp isl6207 control vcc drive isl6207 +5v dacout en
isl6207 fn9075 rev 8.00 page 4 of 10 december 2, 2005 absolute maximum ratings thermal information supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 7v input voltage (v en , v pwm ) . . . . . . . . . . . . . . . -0.3v to v cc + 0.3v boot voltage (v boot ). . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 36v boot to phase voltage (v boot-phase ) . . . . . . . . . . . -0.3v to 7v phase voltage . . . . . . . . . . . . . gnd - 0.3v (dc) to v boot + 0.3v . . . . . . . . . gnd - 5v (<100ns pulse width, 10j) to v boot + 0.3v ugate voltage . . . . . . . . . . v phase - 0.3v (dc) to v boot + 0.3v . . . . . . .v phase - 4v (<200ns pulse width, 20j) to v boot + 0.3v lgate voltage . . . . . . . . . . . . . . gnd - 0.3v (dc) to v vcc + 0.3v . . . . . . . . . . . gnd - 2v (<100ns pulse width, 4j) to v vcc + 0.3v ambient temperature range . . . . . . . . . . . . . . . . . . .- 40c to 125c recommended operating conditions ambient temperature range . . . . . . . . . . . . . . . . . . .- 10c to 100c maximum operating junc tion temperature . . . . . . . . . . . . . . 125c supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v 10% thermal resistance (typical) ? ja (c/w) ? jc (c/w) soic package (note 2) . . . . . . . . . . . . 110 n/a qfn package (notes 3, 4). . . . . . . . . . 95 36 maximum junction temperat ure (plastic package) . . . . . . . . 150c maximum storage temperature range . . . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300c (soic - lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. the phase voltage is capable of withstanding -7v when the boo t pin is at gnd. 2. ? ja is measured with the component mounted on a high effective the rmal conductivity test board in free air. see tech brief tb379 for details. 3. ? ja is measured in free air with the component mounted on a high e ffective thermal conductivity t est board with direct attach f eatures. see tech brief tb379. 4. for ? jc , the case temp location is the center of the exposed metal p ad on the package underside. electrical specifications recommended operating conditions, unless otherwise noted. parameter symbol test conditions min typ max units vcc supply current bias supply current i vcc en = low - - 5.0 ? a bias supply current i vcc pwm pin floating, v vcc = 5v - 30 - ? a bootstrap diode forward voltage v f v vcc = 5v, forward bias current = 2ma 0.45 0.60 0.65 v pwm input input current i pwm v pwm = 5v - 250 - ? a v pwm = 0v - -250 - ? a pwm three-state rising threshold v vcc = 5v - - 1.7 v pwm three-state falling threshold v vcc = 5v 3.3 - - v three-state shutdown holdoff time v vcc = 5v, temperature = 25c - 300 - ns en input en low threshold 1.0 - - v en high threshold --2.0v switching time ugate rise time (note 5) t rugate v vcc = 5v, 3nf load - 8 - ns lgate rise time (note 5) t rlgate v vcc = 5v, 3nf load - 8 - ns ugate fall time (note 5) t fugate v vcc = 5v, 3nf load - 8 - ns lgate fall time (note 5) t flgate v vcc = 5v, 3nf load - 4 - ns ugate turn-off propagation delay t pdlugate v vcc = 5v, outputs unloaded - 18 - ns lgate turn-off propagation delay t pdllgate v vcc = 5v, outputs unloaded - 15 - ns
isl6207 fn9075 rev 8.00 page 5 of 10 december 2, 2005 functional pin description ugate (pin 1 for soic-8, pin 8 for qfn) the ugate pin is t he upper gate drive output. connect to the gate of hi gh-side power n-channel mosfet. boot (pin 2 for soic-8, pin 1 for qfn) boot is the floating bootstrap supply pin for the upper gate drive. connect the bootstrap ca pacitor between this pin and the phase pin. the bootstrap capacitor provides the charge to turn on the upper mosfet. see the bootstrap diode and capacitor section under des cription for guidance in choosing the appropria te capacitor value. pwm (pin 3 for soic-8, pin 2 for qfn) the pwm signal is t he control input for t he driver. the pwm signal can enter three distinc t states during operation, see th e three-state pwm input section under description for further details. connect this pin to the pwm output of the controller. in addition, place a 500k ? resistor to ground from this pin. this allows for proper three-state operation under all start-up conditions. gnd (pin 4 for soic-8, pin 3 for qfn) gnd is the ground pin. all signals are referenced to this node. lgate (pin 5 for soic-8, pin 4 for qfn) lgate is the lower gate drive output. connect to gate of the low-side power n-channel mosfet. vcc (pin 6 for soic-8, pin 5 for qfn) connect the vcc pin to a +5v bias supply. place a high quality bypass capacitor from this pin to gnd. en (pin 7 for soic-8, pin 6 for qfn) en is the enable input pin. c onnect this pin to high to enable, and low to disable, t he ic. when disabled, the ic draws less than 1 ? a bias current. phase (pin 8 for soic-8, pin 7 for qfn) connect the phase pin to the source of the upper mosfet and the drain of the lower mosfet. this pin provides a return path for the upper gate driver. description operation designed for speed, the isl6207 dual mosfet driver controls both high-side and low-side n-channel fets from one externally provided pwm signal. a rising edge on pwm initiates the turn-off of the lower mosfet (see timing diagram) . after a short propagation delay [t pdllgate ], the lower gate begins to fall. typical fall times [t flgate ] are provided in the elec trical specifications section. adaptive shoot-through ci rcuitry monitors the lgate voltage and determines the upper gate delay time [t pdhugate ], based on how quickly the lgate voltage drops below 1v. this prevents both the lower and upper mosfets from conducting simultaneously, or shoot-through. once this delay period is completed, the upp er gate drive begins to rise [t rugate ], and the upper mosfet turns on. ugate turn-on propagation delay t pdhugate v vcc = 5v, outputs unloaded 10 20 30 ns lgate turn-on propagation delay t pdhlgate v vcc = 5v, outputs unloaded 10 20 30 ns output upper drive source resistance r ugate 500ma source current - 1.0 2.5 ? -10c to 85c - 1.0 2.2 ? upper driver source current (note 5) i ugate v ugate-phase = 2.5v - 2.0 - a upper drive sink resistance r ugate 500ma sink current - 1.0 2.5 ? -10c to 85c - 1.0 2.2 ? upper driver sink current (note 5) i ugate v ugate-phase = 2.5v - 2.0 - a lower drive source resistance r lgate 500ma source current - 1.0 2.5 ? -10c to 85c - 1.0 2.2 ? lower driver source current (note 5) i lgate v lgate = 2.5v - 2.0 - a lower drive sink resistance r lgate 500ma sink current - 0.4 1.0 ? -10c to 85c - 0.4 0.8 ? lower driver sink current (note 5) i lgate v lgate = 2.5v - 4.0 - a note: 5. guaranteed by characterization , not 100% tested in production . electrical specifications recommended operating conditions, unless otherwise noted. (continued) parameter symbol test conditions min typ max units
isl6207 fn9075 rev 8.00 page 6 of 10 december 2, 2005 a falling transition on pwm indicates the turn-off of the upper mosfet and the turn-on of the lower mosfet. a short propagation delay [t pdlugate ] is encountered before the upper gate begins to fall [t fugate ]. again, the adaptive shoot- through circuitry determines the lower gate delay time t pdhlgate . the upper mosfet gate-to-source voltage is monitored, and the lower gate is allowed to rise, after the upper mosfet gate-to-source voltage drops below 1v. the lower gate then rises [t rlgate ], turning on the lower mosfet. this driver is optimized for co nverters with large step down ratio, such as those used in a mobile-computer core voltage regulator. the lower mosfet is usually sized much larger. this driver is optimized for co nverters with large step down compared to the upper mos fet because the lower mosfet conducts for a much l onger time in a switching period. the lower gate driver is therefore sized much larger to meet this application requirement. the 0.4 ? on-resistance and 4a sink current capability enable the lower gate driver to absorb the current injected to the lower gate through the drain-to-gate capaci tor of the lower mos fet and prevent a shoot through caused by the h igh dv/dt of the phase node. three-state pwm input a unique feature of the isl6207 and other inters il drivers is the addition of a shutdown window to the pwm input. if the pwm signal enters and remains within the shutdown window for a set holdoff time, the out put drivers are disabled and both mosfet gates are pull ed and held low. the shutdown state is removed when the pw m signal moves outside the shutdown window. otherwise, t he pwm rising and falling thresholds outlined in the electrical specifications determine when the lower and upper gates are enabled. during start-up, pwm should be in the three-state position (1/2 v cc ). however, with rising v cc , the active tracking elements for pwm are not active until v cc > 1.2v, which leaves pwm in a high impedance (undetermined) state; therefore, a 500k ? resistor must be place from the pwm pin to gnd. adaptive shoot-through protection both drivers incorpo rate adaptive shoot -through protection to prevent upper and lowe r mosfets from conducting simultaneously and shorting the input supply. this is accomplished by ensuring the falling gate has turned off one mosfet before the other is allowed to turn on. during turn-off of the lower mosfet, the lgate voltage is monitored until it reaches a 1v threshold, at which time the ugate is released to rise. adapt ive shoot-through circuitry monitors the upper mosfet gate -to-source voltage during ugate turn-off. once the u pper mosfet gate-to-source voltage has dropped below a threshold of 1v, the lgate is allowed to rise. internal bootstrap diode this driver features an intern al bootstrap schottky diode. simply adding an external capacitor across the boot and phase pins completes the bootstrap circuit. the bootstrap capacitor must have a maximum voltage rating above the maximum bat tery voltage plus 5v. the bootstrap capacitor can be chosen from the following equation: where q gate is the amount of gate charge required to fully charge the gate of the upper mosfet. the ? v boot term is defined as the allowable droop i n the rail of the upper drive. as an example, suppose an upper mosfet has a gate charge, q gate , of 25nc at 5v and also assume the droop in the drive voltage over a pwm cycle is 200mv. one will find that a bootstrap capacitance of at least 0.125 ? f is required. pwm ugate lgate t pdllgate t flgate t pdhugate t rugate t pdlugate t fugate t pdhlgate t rlgate 1v 1v figure 1. timing diagram c boot q gate ? v boot ----------------------- - ?
isl6207 fn9075 rev 8.00 page 7 of 10 december 2, 2005 the next larger standard va lue capacitance is 0.22 ? f. a good quality ceramic capacitor is recommended. power dissipation package power dissipation is mainly a function of the switching frequency and total gate char ge of the selected mosfets. calculating the power dissipati on in the driver for a desired application is critical to ensuring safe operation. exceeding t he maximum allowable power dissipation level will push the ic beyond the maximum recomm ended operating junction temperature of 125c. the m aximum allowable ic power dissipation for the so-8 pack age is approxim ately 800mw. when designing the driver into an application, it is recommended that the following calculation be performed to ensure safe operation at the desired frequency for the selected mosfets. the power dissipated by the driver is approximated as: where f sw is the switching frequen cy of the pwm signal. v u and v l represent the upper and lower gate rail voltage. q u and q l is the upper and lower ga te charge determined by mosfet selection and any external capacitance added to the gate pins. the i ddq v cc product is the quiescent power of the driver and is typically negligible. layout considerations reducing phase ring the parasitic inductances of t he pcb and power devices (both upper and lower fets) could c ause increased phase ringing, which may lead to voltages tha t exceed the absolute maximum rating of the devices. when phase rings below ground, the negative voltage could add charge to the bootstrap capacitor through the internal bootstr ap diode. under worst-case conditions, the added charge coul d overstress the boot and/or phase pins. to prevent this fr om happening, the user should perform a careful layout inspec tion to reduce tr ace inductances , and select low lead inductance mosfets and drivers. d 2 pak and dpak packaged mosfets have high parasitic lead inductances, as opposed to soic-8. if higher inductance mosfets must be used, a schottky diode is recommended across the lower mosfet to c lamp negative phase ring. a good layout would help reduce the ringing on the phase and gate nodes significantly: ? avoid using vias for decoupling components where possible, especially in the boot-to-ph ase path. little or no use of vias for vcc and gnd is also recommended. decoupling loops should be short. ? all power traces (ugate, phase, lgate, gnd, vcc) should be short and wide, and av oid using vias. if vias must be used, two or more via s per layer transition is recommended. ? keep the source of the upper f et as close as thermally possible to the drain of the lower fet. ? keep the connection in betw een the source of lower fet and power ground wide and short. ? input capacitors should be pl aced as close to the drain of the upper fet and the so urce of the lower fet as thermally possible. note: refer to intersil tech bri ef tb447 for more information. 0.0 0.4 0.1 0.2 0.3 0.5 0.6 0.7 0.8 0.9 1.0 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 ? v boot (v) c boot (f) figure 2. bootstrap capacitance vs boot ripple voltage q gate = 100nc 50nc 20nc pf sw 1.5v u q u v l q l + ?? i ddq v cc + = frequency (khz) power (mw) figure 3. power dissipation vs frequency 0800 200 400 600 1000 1200 1400 1600 1800 2000 1000 900 800 700 600 500 400 300 200 100 0 q u =20nc q l =50nc q l =50nc q u =50nc q u =50nc q l =100nc q u =100nc q l =200nc
isl6207 fn9075 rev 8.00 page 8 of 10 december 2, 2005 thermal management for maximum thermal performa nce in high current, high switching frequency applications , connecting the thermal pad of the qfn part to the power ground with multiple vias, or placing a low noise copper pla ne underneath the soic part is recommended. this heat spreading allows the part to achieve its full thermal potential. suppressing mosfet gate leakage with vcc at ground potential, ugate and lgate are high impedance. in this state, any str ay leakage has the potential t o deliver charge to either gate. i f ugate receives sufficient charge to bias the dev ice on (note: interna l circuitry prevents leakage currents from charging above 1.8v), a low impedance path will be connected bet ween the mosfet drain and phase. if the input power supply is present and active, the system could see pot entially damaging cu rrents. worst-case leakage currents are on the orde r of pico-amps; therefore, a 10k ? resistor, connected from ugate to phase, is more than sufficient to bleed off any stra y leakage current . this resisto r will not affect the normal perfor mance of the driver or reduce its efficiency.
isl6207 fn9075 rev 8.00 page 9 of 10 december 2, 2005 quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) l8.3x3 8 lead quad flat no-lead plastic package (compliant to jedec mo-220veec issue c) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.23 0.28 0.38 5, 8 d 3.00 bsc - d1 2.75 bsc 9 d2 0.25 1.10 1.25 7, 8 e 3.00 bsc - e1 2.75 bsc 9 e2 0.25 1.10 1.25 7, 8 e 0.65 bsc - k0.25 - - l 0.35 0.60 0.75 8 l1 - - 0.15 10 n82 nd 2 3 ne 2 3 p- -0.609 ? --129 rev. 1 10/02 notes: intersil lead free products employ special lead free material s ets; molding compounds / die attach materials and 100% matte tin pla te termination finish, which is compatible with both snpb and lead free soldering operations. intersil lead free products are msl class ified at lead free peak reflow temperatures that meet or exceed the lead free requirements of ipc/jedec j std-020b. 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in mill imeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measure d between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but m ust be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are for the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provid ed to assist with pcb land patte rn design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & ? are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of t he package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.
fn9075 rev 8.00 page 10 of 10 december 2, 2005 isl6207 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas ll c 2002-2005. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. small outline plast ic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m ? notes: 1. symbols are defined in the mo series symbol list in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension d does not include mold flash, protrusions or gat e burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm ( 0.006 inch) per side. 4. dimension e does not include interlead flash or protrusions . inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. l is the length of terminal for soldering to a substrate. 7. n is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width b, as measured 0.36mm (0.014 inch) or greate r above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millime ter. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 ? 0 8 0 8 - rev. 1 6/05
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